The inventive concept relates to semiconductor devices, semiconductor systems, and method of operating same.
The term Peripheral Component Interconnect (PCI) denotes an evolving body of technical specifications associated with the inter-communication of data between electronic devices. PCI express (PCIe) is an extension of PCI and provides interface protocols that are widely used in the computing industry to facilitate high-speed data transmission between semiconductor devices, or devices included within a semiconductor system. The PCIe interface protocol is well documented as one type of serial data transmission interface protocol. Accordingly, certain PCIe technical specifications, such as the “PCI Express Base Specification Revision 3.1a” published by an organization called PCI SIG may be readily obtained. (Reference e.g., https://pcisig.com/). Hereafter, all pertinent documentation conventionally accessible to those skilled in the art, wholly or in part and including related forthcoming updates, will be termed “the PCIe technical specification.”
As described in considerable detail in the PCIe technical specifications, PCIe technology provides a bidirectional connection that may be used to simultaneously transmit and receive data. In this context, the term “simultaneously” means that a period during which a PCIe capable device transmits data overlaps at least in part a period during which it receives data. The bidirectional connection may include a simplex transmitting path and a simplex receiving path. In order to emphasize such a structure, the bidirectional connection model defined by the PCIe interface protocol may also referred to as a dual-simplex connection model. With the foregoing in mind, a device may alternately be said to be “PCIe enabled”, “PCIe capable”, or capable of “operating in a PCIe environment” where features and performance specified by the PCIe technical specification are substantially incorporated.
The transmitting and receiving paths between PCIe capable devices are termed a “link”, where a link includes at least one pair of transmitting and receiving paths. Here, the transmitting and receiving paths constituting one such “pair” may be termed a “lane”. In this regard, a number of lanes included within a link is defined as a corresponding “link width”.
In order for PCIe devices to transmit and receive data, an initialization routine for defining (or “setting”) a link in a physical layer of the PCIe interface protocol must be executed. However, successful execution of the initialization routine is not guaranteed, and the setting of one or more lanes may fail. For example, a lane may not be set during the initialization routine if a data transmitting path cannot be established. In the event of a “failed lane”, the PCIe device(s) should establish a link using one or more other lane(s).